Before an integrated circuit (IC) may be used in an application, it is typically necessary to verify the proper functionality and timing of components within each input/output (I/O) circuit of the IC. Verifying the functionality of an IC is typically accomplished by placing the IC on an external tester, also known as an Automated Test Equipment (ATE), which may include multiple Parametric Test Units (PMUs). An external tester typically includes a tester channel for each I/O pin on the IC. Subsequently, each I/O buffer coupled to an I/O pin is tested for functionality, timing, performance, etc. However, there are often problems associated with testing an IC in this manner. One problem is that testing each I/O pin on an IC is often expensive due to test equipment costs. Another problem is that the speed of the test equipment is typically not fast enough to keep pace with the IC performance requirements. Moreover, many existing test equipment are not capable of testing high-speed source synchronous systems.
A second approach for testing ICs containing I/Os involves using characterization and performing limited testing with a tester. Some manufacturers of ICs characterize their I/Os and then later, when in production, test merely simple direct current (DC) parameters for selectively sampled I/Os. This approach has become increasingly insufficient due to large number of device pins and smaller geometries that lead to more defects in the I/Os.
A third approach for testing ICs containing I/Os involves using on-chip Design for Testing (DFT) and Built-In Self-Test (BIST). Some companies, typically Integrated Device Manufacturers (IDMs) and some larger fabless companies, use in-house approaches including DFT/BIST. Some approaches are comprehensive, but others are ad hoc and may be difficult to extend to new classes of I/Os and/or new process technologies. Further, using BIST for testing of digital chips provides superior yield and predictable performance. When timing tests, such as I/O timing tests, are to be performed on a device in embedded mode using mostly self-generated signals, it is particularly important that the circuitry provides good performance without large on-chip area demands such as may arise out of excessive circuit complexity.
IEEE 1149.1 (a standard from the Institute of Electrical and Electronic Engineers) is intended for testing of device interconnects, such as printed circuit board (PCB) testing. It is possible to use generic IEEE 1149.1 compliant digital boundary modules for communicating data with I/Os, but that can result in excessively extended test times, too large a tester vector memory requirement, and/or a need for significant on-chip memory such as to store intermediate test results. IEEE 1149.4 (a related IEEE standard) provides for automatic test of analog circuit subsystems but has several disadvantages and limitations. For example, it requires at least two external test point connections (pins) dedicated for testing, and continuous boundary buses. These requirements may be excessively burdensome.